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Optimizing Dynamic-Threshold DTMOS Device Performance in an SOI Embedded DRAM Technology(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2003年04期
Page:
59-62
Research Field:
Publishing date:

Info

Title:
Optimizing Dynamic-Threshold DTMOS Device Performance in an SOI Embedded DRAM Technology
Author(s):
Kim C S 1;  Burke F 1;  Rambhatla A 1;  Zhao Y 1; 3 ;  Zahurak J 2;  Parke S A 1
( 1. Department of Electrical & Computer Engineering, Boise State University, 83725, Idaho, USA)
( 2. Micron Technology Inc, 83707, Idaho, USA)
( 3. College of Electrical and El ectrionic Engineering, Nanjing Normal University, 210042, Nanjing, PRC)
Keywords:
dynamic- threshold DTMOS device;  SOI;  embedded DRAM technology
PACS:
TN386
DOI:
-
Abstract:
This paper describes the DC and high frequency characteristics of a dynamic threshold DTMOS n- channel device, fabricated within a low- cost CMOS SOC process which also includes high- density embedded DRAM. The DTMOS device design in this process was previously found to be superior to both grounded body ( GB) and floating body ( FB) MOSFETs. This DTMOS device achieves kink- free behavior, with gm = 936LS/Lm, gout= 36 μS/ μm, I on / I off = 210 LA/ 011 pA, S = 67 mV/ dec, and f max = 32 GHz at VDD = 1 V. These DTMOS devices are ex cellent for sub- volt embedded baseband circuits with sufficient performance for RF fron-t end circuits, thus enabling the combination of embedded DRAM, digital, analog, and RF circuit cores in, ultra- low- power , low- cost SOCs.

References:

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Last Update: 2013-04-29