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USB 2.0 Device Controller IP Core For Verilog HDL Designs(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2003年04期
Page:
66-70
Research Field:
Publishing date:

Info

Title:
USB 2.0 Device Controller IP Core For Verilog HDL Designs
Author(s):
Zhou Fang;  Wu Ning
College of information science & technology, NUAA, 210016, Nanjing, PRC
Keywords:
USB;  IP core;  Verilog HDL
PACS:
TN402
DOI:
-
Abstract:
A USB 2. 0 device controller IP core design method is introduced in this paper. The function of controller is first summarized, and internal structure modules are explained. Then the controller. s interface with other external IC is introduced. At last UTMI interface, PL, Memory Interface and Arbiter, Control/ status registers, and realize the controller IP core by verilog HDL in Xilinx ISE are analyzed and designed.

References:

[ 1] Compag, Hewlet-t Packard, Intel, et al . Universal Serial Bus Specification Revision 210 [ DB/ OL] . http: / / www. usb. org/ deve-lopers/ docs/ usb- 20. zip, 2002- 12- 21/ 2003- 08.
[ 2] Intel Corporation. USB 210 Transceiver Macrocell Interface Specification Version 1105 [ DB/ OL] . http: / / www. intel. com/ techno-logy/ usb/ download/ 2- 0- Xcvr- Macrocell1 - - 05. pdf, 2001- 03- 29/ 2003- 08.
[ 3] Agere Systems Inc Semiconductors. USS2x1 Data Sheet [ DB/ OL] . http: / /www. agere. com/ client/ docs/ PB00029- 5. pdf, 2002- 10/ 2003- 08.
[ 4] Rudolf Usselmann. USB Function IP Core Rev 11 5 [ DB/ OL] . http: / / www. opencores. org, 2002- 01/ 2003- 08.
[ 5] Xilinx Inc. ISE 4 User Guide [ DB/ OL] . http: / / www. xilinx. com/ support/ sw- manuals/ xilinx6/ index- htm, 2001/ 2003- 08.

Memo

Memo:
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Last Update: 2013-04-29