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High-Gain DSSS Cascaded System Design Based on FPGA(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2007年02期
Page:
53-57
Research Field:
Publishing date:

Info

Title:
High-Gain DSSS Cascaded System Design Based on FPGA
Author(s):
Zhu Qiuming; Cao Zhen; Xu Dazhuan
College of Information Science and Techonology,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China
Keywords:
DSSS;  FPGA;  ascade;  high-ga in
PACS:
TN791
DOI:
-
Abstract:
A longw ith the length o f PN( PeseudoNo ise) code in trad itional DSSS ( Direct Sequence Spread Spectrum) system increasing , the system w ill need much m ore hardware resources and much faster com puting capability. A new cascaded a rchitec ture based on FPGA is introduced to rea lize h igh- ga in DSSS system . To reduce hardw are resources and improve processing speed, this design used tw o orm ore sho rt PN code instead o f one traditiona l long PN code to realizem odu lation and dem odu lation. Resu lts o f analysis and simu la tion showed if w e choose short PN codes reasonab ly , th is cascaded system s’ perform ance is c lose to the trad itiona l sing le system. Bu t it ism uch better in hardw are resource consum ption and search ing tim e. In the end, a DSSS system w as finished in FPGA to va lida te th is cascaded design.

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Last Update: 2013-04-29