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The Design of Physical Coding Sublayer Circuit for Ten-Gigabit Ethernet(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2003年04期
Page:
75-78
Research Field:
Publishing date:

Info

Title:
The Design of Physical Coding Sublayer Circuit for Ten-Gigabit Ethernet
Author(s):
Fei Ruixia;  Zhu En;  Zhao Wenhu;  Wang Zhigong
Institute of RF OE ICs, Southeast University, 210096, Nanjing, PRC
Keywords:
synchronize;  64B/ 66B decode;  parallel;  descrambler
PACS:
TN402
DOI:
-
Abstract:
Based on the protocol of ten gigabit Ethernet 10 G BASE-R, the circuit of the physical coding sublayer is designed. The circuit. s inputs are 16 644.53Mb/ s parallel data, and it. s outputs are 72 156.25Mb/ s parallel data. Using 0118 Lm CMOS, the circuit is realized in full custome.

References:

[ 1] 王志功. 光纤通信集成电路设计[M] . 北京: 高等教育出版社, 2003.
[ 2] Jan M Rabaey. 数字集成电路设计透视[M] . 北京: 清华大学出版社, 1999.
[ 3] 许建生. 万兆以太网实现全网技术统一化[ EB/ OL] . http: / / wwwO. ccidnet. com/ tech/ paper/ 2001/ 02/ 14/ 58- 1674. html#, 2001- 02- 14.

Memo

Memo:
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Last Update: 2013-04-29