|Table of Contents|

A Design of Two-Channel Router for Network on Chip Based on System Level(PDF)

南京师范大学学报(工程技术版)[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2012年01期
Page:
52-56
Research Field:
Publishing date:

Info

Title:
A Design of Two-Channel Router for Network on Chip Based on System Level
Author(s):
Duan LifenWu Ning
College of Electronic Information Engineering,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China
Keywords:
network on chiptwo-channel routerSystemC
PACS:
TN47
DOI:
-
Abstract:
To improve the parallel processing ability of router and reduce the transmitting delay,this paper proposes and designs a two-channel router on system level. This router has two channels,one is GT channel for GT data packets, which adopts virtual channel switch technology,the other is BE channel for BE data packets,which adopts wormholes exchange technology. These two channels are independent on signal,storage,control and transmission. It is constructed on the SystemC platform,and adopts the XY-dimensional routing algorithm,the polling arbitration and the switch control fabric to realize the GT data packets and BE data packets transmitting parallel.

References:

[1]Chai Song,Wu Chang,Li Yubai,et al. A NoC simulation and verification platform based on systemC[C]/ /2008 Internaltional Conference on Computer Science and Software Engineering. Wuhan,2008: 423-426.
[2]Patooghy A,Miremadi S G. XYX: a power and performance efficient fault-tolerant routing algorithm for network on chip[C]/ / Proceedings of the 2009 17th International Conference on Parallel,Distributed and Network-based Processing. Germany: Weimar, 2009: 245-251.
[3]Robert Mullins,Andrew West,Simon Moore. The design and implementation of a low-latency on-chip network[C]/ /Asia and South Pacific Design Automation Conference ( ASP-DAC) . UK: Cambridge University,2006.
[4]万玉鹏,吴宁. NoC 路由单元的系统级设计[J]. 苏州科技学院学报: 工程技术版, 2009, 22( 2) : 61-64. Wan Yupeng,Wu Ning. A design of NoC router based on system level[J]. Journal of University of Scienc and Technology of Suzhou: Engineering and Technolog Edition,2009,22( 2) : 61-64. ( in Chinese)
[5]岳培培,陈杰,刘建,等. 应用于片上网络的双通道路由器[J]. 电子科技大学学报, 2009,38( 2) : 309-312. Yue Peipei,Chen Jie,Liu Jian,et al. Two-channel router for networks-on-chip[J]. Journal of UEST of China,2009,38 ( 2) : 309-312. ( in Chinese)
[6]吴飞. 片上网络适配单元的设计与实现[D]. 南京: 南京航空航天大学: 信息科学与技术学院, 2007. Wu Fei. Design and implementation of adaper for network on chip[D]. Nanjing: College of Information Science and Technology, Nanjing University of Aeronautics and Astronautics,2007. ( in Chinese)
[7]Srinivasan Murali,Luca Benini. Analysis of error recovery schemes for networks on chips[J]. Design and Test of Computers, 2005,22( 5) : 434-442.

Memo

Memo:
-
Last Update: 2013-03-11