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Source/Drain Optimization of the Dynamic-Threshold DTMOS Device in a 0.15μm SOI Embedded DRAM Technology(PDF)

南京师范大学学报(工程技术版)[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2003年04期
Page:
63-65
Research Field:
Publishing date:

Info

Title:
Source/Drain Optimization of the Dynamic-Threshold DTMOS Device in a 0.15μm SOI Embedded DRAM Technology
Author(s):
Burke F 1 Rambhatla A 1 Zahurak J 2 Parke S A
( 1. Department of Electrical & Computer Engineering, Boise State University, 83725, Idaho, USA)
( 2. Micron Technology Inc, 83725, Idaho, USA)
Keywords:
dynamic- threshold DTMOS device source/ drain embedded DRAM technology
PACS:
TN402
DOI:
-
Abstract:
This paper describes experimental results used to optimize the source/ drain implant design of a dynamic threshold DTMOS n- channel device, fabricated within a low- cost 0.15 Lm SOI CMOS System-On-Chip process, which also included high- density embedded DRAM. A shallower , lower dose S/ D implant was found to lower the body resistance and DIBL, thus increasing the dynamic body effect. The DTMOS device design in this process was previously found to be super ior to both grounded body ( GB) and floating body ( FB) operation[ 1] , with I on = 656 μA/ μm, I of f= 3 pA/ Lm, S = 64 mV/ dec, and Gm = 1 690μS/Lm at Vdd = 1.0 V. This DTMOS device was also previously shown to have excellent analog and RF performance, with Fmax = 32 GHz. These characteristics permit embedded ultra- low- voltage analog circuits and RF fron-t end circuits in combination with embedded DRAM cores for ultra- low- power, low- cost SOCs.

References:

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[ 4] Ferle-t Cavrois V, Bracale A, Fel N, et al . High frequency characterization of SOI dynamic throshold voltageMOS ( DTMOS) transistors[A] . IEEE SOI Conference, 1999. 24~ 25.
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[ 6] Yagishita A, Saito T, Inumiya S, et al. Dynamic threshold voltage damascene metal gate MOSFET( DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristics[ A] . International Electron Device Meeting, 2000. 663~ 666.

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Last Update: 2013-04-29