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Architecture Design for Huarui-2 SoC Based on ESL(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2016年04期
Page:
69-
Research Field:
计算机与信息工程
Publishing date:

Info

Title:
Architecture Design for Huarui-2 SoC Based on ESL
Author(s):
Liu Jing; Zhou Haibin
Nanjing Research Institute of Electronics Technology,Nanjing 210039,China
Keywords:
Huarui-2; SoC; ESL; architecture design
PACS:
TP391.9
DOI:
10.3969/j.issn.1672-1292.2016.04.012
Abstract:
Huarui-2 is a 8 cores high-performance embedded processor(based on cmos 40nm)developed by NRIET. Huarui-2 is constructed by 8-core DSP,AXI bus,PCIE/DDR3 and other high-speed interface. Given the SoC complexity,we need to use the electronic system level(ESL)solution,and determine SoC-level architecture. ESL methodology has been adopted by more and more complex SoC designs. Designers can build and verify their SoC platforms rapidly,do architecture exploration to know the system performance with the generated Virtual Prototype with the scalable TLM modeling method. Via Synopsys ESL solution,we create different architectures and run typical radar signal processing applications based on the architectures. By analyzing the processing time and bus pressure,we ultimately determine the best architecture of Huarui-2.

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Memo

Memo:
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Last Update: 2016-12-31