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Static and Dynamic ESD Testing and Failure Analysis for 40 nm IC Products(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2019年04期
Page:
8-12
Research Field:
2019全国集成电路可靠性学术会议专栏
Publishing date:

Info

Title:
Static and Dynamic ESD Testing and Failure Analysis for 40 nm IC Products
Author(s):
Zhao Junwei1; 2; Qiao Yanbin1; 2; Zhang Haifeng1; 2; Chen Yanning1; 2; Li Jiewei1; 2; Fu Rongjie1; 2
(1.State Grid Key Laboratory of Power Industrial Chip Design and Analysis Technology,Beijing Smart-ChipMicroeletronics Technology Co.,Ltd.,Beijing 100192,China)2.Beijing Engineering Research Center of High-reliability IC with Power Industrial Grade,Beijing Smart-ChipMicroeletronics Technology Co.,Ltd.,Beijing 100192,China)
Keywords:
electrical discharge; ESD protection; charged device model; OBIRCH
PACS:
TN406
DOI:
10.3969/j.issn.1672-1292.2019.04.002
Abstract:
Considering the complex electromagnetic environment faced by the use of electronic devices in the power grid,the paper introduces the test of ESD protection ability under static and dynamic conditions. ESD charged device model(CDM)failure phenomenon and location method of failure position are analyzed. Based on LQFP64 package form IC,using 40 nm,the ESD test method and failure phenomenon determination process is discussed in detail. OBIRCH and SEM are used to locate the failure position and analyze the failure point accurately. Through the detailed test results,the failure mechanism of the transistors in the ESD protection circuit is analyzed. Under the positive feedback of the decrease of resistance and the increase of current density,the transistors in the protection circuit will fuse,which leads to the failure of the ESD protection circuit.

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Last Update: 2019-12-31