[1]Burke F,Rambhatla A,Zahurak J,等.基于0.15微米SOI嵌入式DRAM技术的动态钳制电位DTMOS器件源极与漏极的优化设计(英文)[J].南京师范大学学报(工程技术版),2003,03(04):063-65.
　Burke F,Rambhatla A,Zahurak J,et al.Source/Drain Optimization of the Dynamic-Threshold DTMOS Device in a 0.15μm SOI Embedded DRAM Technology[J].Journal of Nanjing Normal University(Engineering and Technology),2003,03(04):063-65.
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基于0.15微米SOI嵌入式DRAM技术的动态钳制电位DTMOS器件源极与漏极的优化设计(英文)
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南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

卷:
03卷
期数:
2003年04期
页码:
063-65
栏目:
出版日期:
2003-12-30

文章信息/Info

Title:
Source/Drain Optimization of the Dynamic-Threshold DTMOS Device in a 0.15μm SOI Embedded DRAM Technology
作者:
Burke F1 ;  Rambhatla A1 ;  Zahurak J2 ;  Parke S A1
( 1. 美国爱达荷州BOISE 州立大学电气与计算机系, 83725, 爱达荷州)
( 2. 美国Micron 公司, 83701, 爱达荷州)
Author(s):
Burke F 1;  Rambhatla A 1;  Zahurak J 2;  Parke S A
( 1. Department of Electrical & Computer Engineering, Boise State University, 83725, Idaho, USA)
( 2. Micron Technology Inc, 83725, Idaho, USA)
关键词:
动态钳制电位DTMOS器件;  嵌入式DRAM技术;  系统集成芯片
Keywords:
dynamic- threshold DTMOS device;  source/ drain;  embedded DRAM technology
分类号:
TN402
摘要:
描述了用以进行n 沟道动态电位DTMOS半导体器件源极 /漏极载流子注入优化设计的实验结果 ,该器件制造采用了低成本 0 .15微米SOI和SOC(system on chip ,系统集成芯片 )技术 ,同时也包含了高密度嵌入式DRAM技术 .实验结果表明 ,本器件可用来作为嵌入式超低压模拟电路和射频前端电路的混合电路芯片 ,并与嵌入式DRAM核心技术一起 ,作为超低压、低成本SOC(系统集成芯片 )使用
Abstract:
This paper describes experimental results used to optimize the source/ drain implant design of a dynamic threshold DTMOS n- channel device, fabricated within a low- cost 0.15 Lm SOI CMOS System-On-Chip process, which also included high- density embedded DRAM. A shallower , lower dose S/ D implant was found to lower the body resistance and DIBL, thus increasing the dynamic body effect. The DTMOS device design in this process was previously found to be super ior to both grounded body ( GB) and floating body ( FB) operation[ 1] , with I on = 656 μA/ μm, I of f= 3 pA/ Lm, S = 64 mV/ dec, and Gm = 1 690μS/Lm at Vdd = 1.0 V. This DTMOS device was also previously shown to have excellent analog and RF performance, with Fmax = 32 GHz. These characteristics permit embedded ultra- low- voltage analog circuits and RF fron-t end circuits in combination with embedded DRAM cores for ultra- low- power, low- cost SOCs.

参考文献/References:

[ 1] Goldman D, Degregorio K, Kim C S, et al . 0. 15Lm SOI DRAM technology incorporating sub-volt dynamic threshold devices for embedded mixed- signal & RF circuits[ A] . IEEE SOI Cnoference, 2001. 97~ 98.
[ 2] Parke S A, Hu C, Ko P K. Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFET[ J] . IEEE EDL, 1993, 14( 5) :234~ 236.
[ 3] Assaderaghi F, Sinitsky D, Parke S, et al . Dynamic threshold-voltage MOSFET ( DTMOS) for ultra- low voltage VLSI[ J] . IEEETED, 1997, 44( 3) : 414~ 422.
[ 4] Ferle-t Cavrois V, Bracale A, Fel N, et al . High frequency characterization of SOI dynamic throshold voltageMOS ( DTMOS) transistors[A] . IEEE SOI Conference, 1999. 24~ 25.
[ 5] Momiyama Y, Hirose T, Kurata H, et al . A 140 GHz f t and 60GHz f max DTMOS integrated with high- performance SOI logil technology[A] . International Electron DevicesMeeting, 2003. 451~ 454.
[ 6] Yagishita A, Saito T, Inumiya S, et al. Dynamic threshold voltage damascene metal gate MOSFET( DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristics[ A] . International Electron Device Meeting, 2000. 663~ 666.

相似文献/References:

[1]Kim C S,Burke F,Rambhatla A,等.SOI嵌入式DRAM技术动态钳制电位DTMOS器件性能的优化设计(英文)[J].南京师范大学学报(工程技术版),2003,03(04):059.
　Kim C S,Burke F,Rambhatla A,et al.Optimizing Dynamic-Threshold DTMOS Device Performance in an SOI Embedded DRAM Technology[J].Journal of Nanjing Normal University(Engineering and Technology),2003,03(04):059.

备注/Memo

备注/Memo:
Founation Items: Support ed by American Nat ional Science Foundat ion Grant EPS-9977454.
Biography: Burke F, Jamaican, born in 1981, Master graduate at department of Electrical& Computer Engineering, Boise State University; his research interest includes IC design, device modeling and Characterization.
更新日期/Last Update: 2013-04-29