[1]赵军伟,乔彦彬,张海峰,等.40 nm IC静态和动态 ESD测试及失效分析[J].南京师范大学学报(工程技术版),2019,19(04):008-12.[doi:10.3969/j.issn.1672-1292.2019.04.002]
 Zhao Junwei,Qiao Yanbin,Zhang Haifeng,et al.Static and Dynamic ESD Testing and Failure Analysis for 40 nm IC Products[J].Journal of Nanjing Normal University(Engineering and Technology),2019,19(04):008-12.[doi:10.3969/j.issn.1672-1292.2019.04.002]
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40 nm IC静态和动态 ESD测试及失效分析
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南京师范大学学报(工程技术版)[ISSN:1006-6977/CN:61-1281/TN]

卷:
19卷
期数:
2019年04期
页码:
008-12
栏目:
2019全国集成电路可靠性学术会议专栏
出版日期:
2019-12-31

文章信息/Info

Title:
Static and Dynamic ESD Testing and Failure Analysis for 40 nm IC Products
文章编号:
1672-1292(2019)04-0008-05
作者:
赵军伟12乔彦彬12张海峰12陈燕宁12李杰伟12符荣杰12
(1.北京智芯微电子科技有限公司,国家电网公司重点实验室 电力芯片设计分析实验室,北京 100192)(2.北京智芯微电子科技有限公司,北京市电力高可靠性集成电路设计工程技术研究中心,北京 100192)
Author(s):
Zhao Junwei12Qiao Yanbin12Zhang Haifeng12Chen Yanning12Li Jiewei12Fu Rongjie12
(1.State Grid Key Laboratory of Power Industrial Chip Design and Analysis Technology,Beijing Smart-ChipMicroeletronics Technology Co.,Ltd.,Beijing 100192,China)2.Beijing Engineering Research Center of High-reliability IC with Power Industrial Grade,Beijing Smart-ChipMicroeletronics Technology Co.,Ltd.,Beijing 100192,China)
关键词:
静电放电静电保护器件充放电模式激光束电阻异常侦测
Keywords:
electrical dischargeESD protectioncharged device modelOBIRCH
分类号:
TN406
DOI:
10.3969/j.issn.1672-1292.2019.04.002
文献标志码:
A
摘要:
结合电网内使用电子器件面临的复杂电磁环境,介绍芯片在静态和动态下静电放电(electrostatic discharge,ESD)的防护能力测试,分析了ESD器件充放电模式(CDM)失效的现象和定位方法. 针对40 nm LQFP64封装芯片,详细介绍ESD测试过程和失效判定分析过程,综合运用激光束电阻异常侦测、扫描电子显微镜等手段完成对失效位置的定位和失效点的精确分析. 通过测试结果分析其失效机理,ESD保护电路中的晶体管,在电阻率下降、电流密度增加导致温度升高的正反馈作用下保护电路中的晶体管发生熔断,从而导致ESD保护电路失效.
Abstract:
Considering the complex electromagnetic environment faced by the use of electronic devices in the power grid,the paper introduces the test of ESD protection ability under static and dynamic conditions. ESD charged device model(CDM)failure phenomenon and location method of failure position are analyzed. Based on LQFP64 package form IC,using 40 nm,the ESD test method and failure phenomenon determination process is discussed in detail. OBIRCH and SEM are used to locate the failure position and analyze the failure point accurately. Through the detailed test results,the failure mechanism of the transistors in the ESD protection circuit is analyzed. Under the positive feedback of the decrease of resistance and the increase of current density,the transistors in the protection circuit will fuse,which leads to the failure of the ESD protection circuit.

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备注/Memo

备注/Memo:
收稿日期:2019-09-10.
基金项目:国家自然科学基金(U1866212).
通讯联系人:赵军伟,工程师,研究方向:芯片可靠性及失效分析等方面的研究. E-mail:zhaojunwei@sgitg.sgcc.com.cn
更新日期/Last Update: 2019-12-31