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ASIC Design of a Novel Structure Asynchronous FIFO(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2005年02期
Page:
14-17
Research Field:
Publishing date:

Info

Title:
ASIC Design of a Novel Structure Asynchronous FIFO
Author(s):
ZHOU Lei;  ZHU Li′an;  SU Junjie;  DING Xiaolei;  ZHAO Mei;  GU Gaowei;  ZHU En
Institute of RF-& OE-ICs, Southeast University, Jiangsu Nanjing 210096, China
Keywords:
asynchronous FIFO ;  ASIC;  unitary sh ift;  buffers
PACS:
TN402
DOI:
-
Abstract:
The paper presents a schem e o f rea lizing nove l asynchronous FIFO ( First In F irst Out) structure c ircuit. In th is schem e, un itary sh ift is used to rea lize data s’ correct read- in and ou tput, and bu ffers are used to store the left data o f un itary sh ift. Th is design is applicable for data transm ission betw een clocks no t in teg ra lmu ltiple. Synchron izer of D triggers in series is used to avo id instability and synchron ize asynchronous signals. Th is c ircuit is designed w ith sem i- custom ASIC ( App lication Spec ific Integrated C ircu it) flow w hich is based on top - down flow and 0. 18μm d ig ita l standa rd ce ll library. The design uses Verilog hardw are language, adopts VCS andM ode lsim to simu la te, Synopsys DC to rea lize log ic synthesis and Apollo II to ach ieve autom atic p lacing and routing. Com pared w ith trad itiona l asynchronous FIFO struc ture, it show s better pe rfo rm ance no t on ly on area ( w ith about ha lf acreage) but on speed ( one th ird faster) as we ll.

References:

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Memo

Memo:
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Last Update: 2013-04-29