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Low-Power Design of Router for NoC With Clock Gating(PDF)

南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

Issue:
2009年03期
Page:
18-21
Research Field:
Publishing date:

Info

Title:
Low-Power Design of Router for NoC With Clock Gating
Author(s):
Zhai Liang; Wu Ning
College of Information Technology Science,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China
Keywords:
c lock gating;  NoC;  Low-Pow er;  router
PACS:
TN47
DOI:
-
Abstract:
Netw ork-on-Ch ip ( NoC) arch itectures are gradually replacing interconnec tion on ch ip, and thus becom ing an a ttractive so lution to address the inter-connect de lay prob lem s in System-on-Chip. H owever, increased pow er d issipation has h indered the w ide-dep loym ent o fNoCs. From Route r, the kerne l unit, on the basis of the study o f the structure o f router on the b -i d im ensiona lM esh ch ip and the techn ique o f clock gating, the pape r proposes a low-pow er design o f Router w ithMode l level C lock gating (M CG) techn iques, by using code to contro l the c lock signal of the Input. Functiona l sim ulation is donew ithM odelSim SE PLUS 6.0 too ls. Resu lts o f synthesis w ith design comp iler o f the synopsy s Inc. show tha t the dynam ic pow er consump tion o f a rou ter is reduced by 11.38% w ith 200MH z operating frequency。

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Last Update: 2013-04-23