[1]翟亮,吴宁.基于门控时钟的片上网络路由单元低功耗设计[J].南京师范大学学报(工程技术版),2009,09(03):018-21.
　Zhai Liang,Wu Ning.Low-Power Design of Router for NoC With Clock Gating[J].Journal of Nanjing Normal University(Engineering and Technology),2009,09(03):018-21.
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基于门控时钟的片上网络路由单元低功耗设计
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南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

卷:
09卷
期数:
2009年03期
页码:
018-21
栏目:
出版日期:
2009-09-30

文章信息/Info

Title:
Low-Power Design of Router for NoC With Clock Gating
作者:
翟亮;吴宁;
南京航空航天大学信息科学与技术学院, 江苏南京210016
Author(s):
Zhai Liang; Wu Ning
College of Information Technology Science,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China
关键词:
门控时钟;  片上网络;  低功耗;  路由单元
Keywords:
c lock gating;  NoC;  Low-Pow er;  router
分类号:
TN47
摘要:
NoC(Network-on-Chip)已经逐渐代替片上总线互连,成为片上系统的解决方案,然而迅速增长的功耗将阻碍NoC的性能与发展.从NoC的核心部件路由单元入手,在研究了二维Mesh下片上网络路由单元的结构和门控时钟技术的基础上,对路由单元功耗最集中的输入端口采用了模块级门控时钟技术进行低功耗设计,通过利用软件判断控制门控使能信号来实现受控端口时钟的通断.在ModelSim SE PLUS 6.0环境下进行路由单元功能仿真,并通过Synopsys公司的Design Compiler工具给出综合结果,路由单元工作频率200MHz,动态功耗51.0457mW,降低了11.38%.
Abstract:
Netw ork-on-Ch ip ( NoC) arch itectures are gradually replacing interconnec tion on ch ip, and thus becom ing an a ttractive so lution to address the inter-connect de lay prob lem s in System-on-Chip. H owever, increased pow er d issipation has h indered the w ide-dep loym ent o fNoCs. From Route r, the kerne l unit, on the basis of the study o f the structure o f router on the b -i d im ensiona lM esh ch ip and the techn ique o f clock gating, the pape r proposes a low-pow er design o f Router w ithMode l level C lock gating (M CG) techn iques, by using code to contro l the c lock signal of the Input. Functiona l sim ulation is donew ithM odelSim SE PLUS 6.0 too ls. Resu lts o f synthesis w ith design comp iler o f the synopsy s Inc. show tha t the dynam ic pow er consump tion o f a rou ter is reduced by 11.38% w ith 200MH z operating frequency。

参考文献/References:

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备注/Memo

备注/Memo:
基金项目: 江苏省自然科学基金( BK2008387)资助项目.
通讯联系人: 吴宁, 教授, 博士生导师, 研究方向: 数字系统理论与技术、电子系统集成与专用集成电路, E-m ail:wunee@ nuaa. edu. cn
更新日期/Last Update: 2013-04-23