[1]Kim C S,Burke F,Rambhatla A,等.SOI嵌入式DRAM技术动态钳制电位DTMOS器件性能的优化设计(英文)[J].南京师范大学学报(工程技术版),2003,03(04):059-62.
　Kim C S,Burke F,Rambhatla A,et al.Optimizing Dynamic-Threshold DTMOS Device Performance in an SOI Embedded DRAM Technology[J].Journal of Nanjing Normal University(Engineering and Technology),2003,03(04):059-62.
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SOI嵌入式DRAM技术动态钳制电位DTMOS器件性能的优化设计(英文)
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南京师范大学学报（工程技术版）[ISSN:1006-6977/CN:61-1281/TN]

卷:
03卷
期数:
2003年04期
页码:
059-62
栏目:
出版日期:
2003-12-30

文章信息/Info

Title:
Optimizing Dynamic-Threshold DTMOS Device Performance in an SOI Embedded DRAM Technology
作者:
Kim C S1 ;  Burke F1 ;  Rambhatla A1 ;  赵阳1;  3 ;  Zahurak J3 ;  Parke S A1
( 1. 美国爱达荷州BOISE 州立大学电气与计算机系, 83725, 爱达荷州)
( 2. 美国Micron 公司, 83707, 爱达荷州)
( 3. 南京师范大学电气与电子工程学院, 210042, 南京)
Author(s):
Kim C S 1;  Burke F 1;  Rambhatla A 1;  Zhao Y 1; 3 ;  Zahurak J 2;  Parke S A 1
( 1. Department of Electrical & Computer Engineering, Boise State University, 83725, Idaho, USA)
( 2. Micron Technology Inc, 83707, Idaho, USA)
( 3. College of Electrical and El ectrionic Engineering, Nanjing Normal University, 210042, Nanjing, PRC)
关键词:
动态钳制电位DTMOS器件;  系统集成芯片;  嵌入式DRAM技术
Keywords:
dynamic- threshold DTMOS device;  SOI;  embedded DRAM technology
分类号:
TN386
摘要:
描述了n 沟道动态电位DTMOS半导体器件的直流和高频特性 ,该器件制造采用了低功耗CMOSSOC工艺 ,同时也包含了高密度嵌入式DRAM技术 .在本工作中的DTMOS器件在较早时候就发现性能优于本体接地 (GB)和本体浮地 (FB)的MOSFET器件 .本器件具有无特性曲线缠绕、gm=93 6μS/ μm ,gout=3 6μS/ μm ,Ion/Ioff=2 10 μA/ 0 .1pA ,在Vdd=1V时fmax=3 2GHz的良好特性 ,特别适用于低电压嵌入式基频电路并具有对射频RF前端电路的极佳性能 ,因此可以使嵌入式DRAM、数字电路、模拟电路和RF射频电路混合于一体 ,用在超低功耗、低成本的SOC(系统集成 )芯片系统中
Abstract:
This paper describes the DC and high frequency characteristics of a dynamic threshold DTMOS n- channel device, fabricated within a low- cost CMOS SOC process which also includes high- density embedded DRAM. The DTMOS device design in this process was previously found to be superior to both grounded body ( GB) and floating body ( FB) MOSFETs. This DTMOS device achieves kink- free behavior, with gm = 936LS/Lm, gout= 36 μS/ μm, I on / I off = 210 LA/ 011 pA, S = 67 mV/ dec, and f max = 32 GHz at VDD = 1 V. These DTMOS devices are ex cellent for sub- volt embedded baseband circuits with sufficient performance for RF fron-t end circuits, thus enabling the combination of embedded DRAM, digital, analog, and RF circuit cores in, ultra- low- power , low- cost SOCs.

参考文献/References:

[ 1] Goldman D, Degregorio K, Kim C S, et al . 0. 15Lm SOI DRAM technology incorporating sub-volt dynamic threshold devices for embedded mixed- signal & RF circuits[ A] . IEEE SOI Cnoference, 2001. 97~ 98.
[ 2] Parke S A, Hu C, Ko P K. Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFET[ J] . IEEE EDL, 1993, 14( 5) :234~ 236.
[ 3] Assaderaghi F, Sinitsky D, Parke S, et al . A dynamic threshold Voltage MOSFET ( DTMOS) for ultra- low voltage operation[ A] .International Electron Devices Meeting , 1994. 809~ 812.
[ 4] Assaderaghi F, Sinitsky D, Parke S A, et al . Dynamic threshold- voltage MOSFET ( DTMOS) for ultra- low voltage VLSI[ J] . IEEE TED, 1997, 44( 3) : 414~ 422.
[ 5] Tanaka T, Momiyama Y, Sugii T. Fmax enhancement of dynamic threshold- voltage MOSFET ( DTMOS) under ultra- low supply volt-age[ A] . International Electron Devices Meeting , 1997. 423~ 426.
[ 6] Ferle-t Cavrois V, Bracale A, Fel N, et al . High frequency characterization of SOI dynamic throshold voltageMOS ( DTMOS) transistors[A] . IEEE SOI Conference, 1999. 24~ 25.
[ 7] Momiyama Y, HiroseT, KurataH, et al. A 140 GHz f t and 60 GHz f max DTMOS integrated with high- performance SOI logic technology[A] . International Electron DevicesMeeting, 2003. 451~ 454.
[ 8] Yagishita A, Saito T, Inumiya S, et al. Dynamic threshold voltage damascene metal gate MOSFET( DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristics[ A] . International Electron Device Meeting, 2000. 663~ 666.

相似文献/References:

[1]Burke F,Rambhatla A,Zahurak J,等.基于0.15微米SOI嵌入式DRAM技术的动态钳制电位DTMOS器件源极与漏极的优化设计(英文)[J].南京师范大学学报(工程技术版),2003,03(04):063.
　Burke F,Rambhatla A,Zahurak J,et al.Source/Drain Optimization of the Dynamic-Threshold DTMOS Device in a 0.15μm SOI Embedded DRAM Technology[J].Journal of Nanjing Normal University(Engineering and Technology),2003,03(04):063.

备注/Memo

备注/Memo:
Founation Items: Support ed by American Nat ional Science Foundat ion Grant EPS-9977454.
Biography: Kim C S, Korean, born in 1968, postdoctoral in department of Elect rical& Computer Engineering, Boise St ate University; his research interest includes IC design, device model ing and characterization.
更新日期/Last Update: 2013-04-29